An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems
Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina.
| Main Authors: | , , , |
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| Format: | conferenceObject |
| Language: | eng |
| Published: |
2024
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| Online Access: | http://hdl.handle.net/11086/553345 |
| _version_ | 1808636209371545600 |
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| author | Sanchez, Raúl M. Reyes, Benjamín T. Pola, Ariel L. Hueda, Mario R. |
| author_facet | Sanchez, Raúl M. Reyes, Benjamín T. Pola, Ariel L. Hueda, Mario R. |
| author_sort | Sanchez, Raúl M. |
| collection | Repositorio Digital Universitario |
| description | Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina. |
| format | conferenceObject |
| id | rdu-unc.553345 |
| institution | Universidad Nacional de Cordoba |
| language | eng |
| publishDate | 2024 |
| record_format | dspace |
| spelling | rdu-unc.5533452024-08-23T06:22:40Z An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems Sanchez, Raúl M. Reyes, Benjamín T. Pola, Ariel L. Hueda, Mario R. Digital Communication FPGA Mixed-signal Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina. Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. Fil: Pola, Ariel L. Fundación Fulgor; Argentina. Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm. http://dx.doi.org/10.1109/LASCAS.2016.7451041 Fil: Sanchez, Raúl M. Fundación Fulgor; Argentina. Fil: Reyes, Benjamín T. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. Fil: Pola, Ariel L. Fundación Fulgor; Argentina. Fil: Hueda, Mario R. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. Telecomunicaciones 2024-08-22T13:48:24Z 2024-08-22T13:48:24Z 2016 conferenceObject http://hdl.handle.net/11086/553345 eng Attribution-NonCommercial-ShareAlike 4.0 International http://creativecommons.org/licenses/by-nc-sa/4.0/ Impreso; Electrónico y/o Digital |
| spellingShingle | Digital Communication FPGA Mixed-signal Sanchez, Raúl M. Reyes, Benjamín T. Pola, Ariel L. Hueda, Mario R. An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title | An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title_full | An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title_fullStr | An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title_full_unstemmed | An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title_short | An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems |
| title_sort | fpga based emulation platform for evaluation of time interleaved adc calibration systems |
| topic | Digital Communication FPGA Mixed-signal |
| url | http://hdl.handle.net/11086/553345 |
| work_keys_str_mv | AT sanchezraulm anfpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT reyesbenjamint anfpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT polaariell anfpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT huedamarior anfpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT sanchezraulm fpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT reyesbenjamint fpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT polaariell fpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems AT huedamarior fpgabasedemulationplatformforevaluationoftimeinterleavedadccalibrationsystems |