Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture
Fil: Zerbini, Carlos A. Universidad Tecnológica Nacional. Departamento de Ingeniería Electrónica; Argentina.
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| Format: | conferenceObject |
| Language: | eng |
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2022
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| Online Access: | http://hdl.handle.net/11086/28727 |
| _version_ | 1801213370722942976 |
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| author | Zerbini, Carlos A. Finochietto, Jorge M. |
| author_facet | Zerbini, Carlos A. Finochietto, Jorge M. |
| author_sort | Zerbini, Carlos A. |
| collection | Repositorio Digital Universitario |
| description | Fil: Zerbini, Carlos A. Universidad Tecnológica Nacional. Departamento de Ingeniería Electrónica; Argentina. |
| format | conferenceObject |
| id | rdu-unc.28727 |
| institution | Universidad Nacional de Cordoba |
| language | eng |
| publishDate | 2022 |
| record_format | dspace |
| spelling | rdu-unc.287272022-10-14T10:12:38Z Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture Zerbini, Carlos A. Finochietto, Jorge M. Pipeline processing Field-programmable Hardware-based Classification architectures Fil: Zerbini, Carlos A. Universidad Tecnológica Nacional. Departamento de Ingeniería Electrónica; Argentina. Fil: Finochietto, Jorge M. Universidad Nacional de Córdoba. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an area of extensive research. Even if Field Programmable Logic Arrays (FPGAs) have emerged as an interesting technology for implementing these architectures, existing proposals either exploit maximal concurrency with unbounded resource consumption, or base the architecture on distributed RAM memory-based schemes which strongly undervalues FPGA capabilities. Moreover, most of these proposals target best-match classification and are not suited for high-speed updates of classification rulesets. In this paper, we propose a new approach which exploits rich logic resources available in modern FPGAs while reducing memory consumption. Our architecture is conceived for multi-match classification, and its mapping methodology is naturally suited for high-speed, simple updating of the classification ruleset. Analytical evaluation and implementation results of our architecture are promising, demonstrating that it is suitable for line speed processing with balanced resource consumption. With additional optimizations, our proposal has the potential to be integrated into network processing architectures demanding all aforementioned features. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6602301 Fil: Zerbini, Carlos A. Universidad Tecnológica Nacional. Departamento de Ingeniería Electrónica; Argentina. Fil: Finochietto, Jorge M. Universidad Nacional de Córdoba. Consejo Nacional de Investigaciones Científicas y Técnicas. Laboratorio de Comunicaciones Digitales; Argentina. Ingeniería de Sistemas y Comunicaciones 2022-10-13T14:58:56Z 2022-10-13T14:58:56Z 2013 conferenceObject 2325-5552 http://hdl.handle.net/11086/28727 eng Attribution-NonCommercial-ShareAlike 4.0 International https://creativecommons.org/licenses/by-nc-sa/4.0/ Electrónico y/o Digital |
| spellingShingle | Pipeline processing Field-programmable Hardware-based Classification architectures Zerbini, Carlos A. Finochietto, Jorge M. Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title | Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title_full | Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title_fullStr | Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title_full_unstemmed | Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title_short | Multi-match Packet Classification on Memory-Logic Trade-off FPGA-based Architecture |
| title_sort | multi match packet classification on memory logic trade off fpga based architecture |
| topic | Pipeline processing Field-programmable Hardware-based Classification architectures |
| url | http://hdl.handle.net/11086/28727 |
| work_keys_str_mv | AT zerbinicarlosa multimatchpacketclassificationonmemorylogictradeofffpgabasedarchitecture AT finochiettojorgem multimatchpacketclassificationonmemorylogictradeofffpgabasedarchitecture |